In an optical receiver that receives an optical signal and obtains a reception output formed from an electrical signal, an optical signal detection circuit (SD: Signal Detect) that determines the presence/absence of optical signal input is used to prevent the optical receiver from outputting unwanted noise in the absence of an optical signal. The optical signal detection circuit generates an optical signal detection signal representing whether an optical signal having a sufficient strength is received, thereby detecting a communication error or performing squelch control to cut off noise output from a limiting amplifier LA under no-signal conditions.
FIG. 9 is a block diagram showing the arrangement of a conventional optical receiver (see, for example, patent literature 1). In an optical receiver 200, a photodiode PD photoelectrically converts an optical signal Pin formed from a pulse train into a photocurrent signal Iin. A transimpedance amplifier TIA serving as a preamplifier amplifies the photocurrent signal Iin and outputs an electrical signal Tout. The electrical signal Tout output from the transimpedance amplifier TIA is input to a limiting amplifier LA serving as a post-amplifier. The limiting amplifier LA amplifies the electrical signal Tout and outputs a reception output Rout having a predetermined amplitude with respect to the optical signals Pin of various strengths. A waveform shaping circuit such as a CDR (Clock Data Recovery) or a timing adjustment circuit is normally provided at the subsequent stage of the limiting amplifier LA so as to extract a clock signal from a data signal included in the reception output Rout or shape the signal waveform into a waveform easy to be handled as a digital signal.
The transimpedance amplifier TIA is AC-coupled to an optical signal detection circuit 20. A positive-phase signal Tout+ and a negative-phase signal Tout− of the electrical signal Tout are input to the optical signal detection circuit 20 via corresponding coupling capacitors C. The optical signal detection circuit 20 includes a comparator 21 that outputs a comparison output signal Cout only when the electrical signal Tout is received, and an SR latch 22 that holds the comparison output signal Cout and converts it into an optical signal detection signal SD formed from a DC signal. The SR latch 22 cancels holding of the optical signal detection signal SD in accordance with a reset signal RESET. For example, in burst communication represented by a PON system, a PON control IC can output the reset signal RESET at the end of burst packet reception.
For example, the optical signal detection signal SD is used for squelch control, and the squelch is closed during the time from reception of the reset signal RESET up to reception of the next burst signal. This makes it possible to prevent noise output from the limiting amplifier LA. When the next burst signal is received, the squelch can be opened to return to a normal reception state.
FIG. 10 is a circuit diagram showing the arrangement of the comparator 21 used in the optical signal detection circuit according to the related art. The comparator 21 includes a first-stage bias circuit 21A, a first-stage amplification circuit 21B, a first-stage emitter follower circuit 21C, and a next-stage amplification circuit 21D.
The first-stage bias circuit 21A AC-coupled to the transimpedance amplifier TIA includes resistors R21 and R22 and resistors R23 and R24, which divide a power supply potential Vcc. The first-stage bias circuit 21A gives a DC bias to each of the positive-phase signal Tout+ and the negative-phase signal Tout− of the electrical signal Tout whose DC components are cut by the corresponding coupling capacitors C. The biased positive-phase signal Tout+ and negative-phase signal Tout− are input to a pair of differential transistors Q21 and Q22 of the first-stage amplification circuit 21B, respectively.
The first-stage amplification circuit 21B differentially amplifies the positive-phase signal Tout+ and the negative-phase signal Tout− of the electrical signal Tout and outputs them to the next-stage amplification circuit 21D via the first-stage emitter follower circuit 21C.
In the first-stage amplification circuit 21B, when load resistors R25 and R26 of the pair of differential transistors Q21 and Q22 are made to have different values, the DC level of the output of the first-stage amplification circuit 21B has an offset voltage.
If the amplitudes of the positive-phase signal Tout+ and the negative-phase signal Tout− input to the first-stage amplification circuit 21B are small, the inverted output from the transistor Q21 and the noninverted output from the transistor Q22 do not cross due to the offset voltage, that is, the first-stage amplification circuit 21B does not form a differential signal. In this case, the next-stage amplification circuit 21D that receives the noninverted output and the inverted output from the first-stage amplification circuit 21B does not output the pulsed comparison output signal Cout.
On the other hand, if the amplitudes of the input positive-phase signal Tout+ and negative-phase signal Tout− are sufficiently large, the inverted output from the transistor Q21 and the noninverted output from the transistor Q22 cross regardless of the presence of the offset voltage. In this case, High level and Low level corresponding to the crossing alternately appear in the comparison output signal Cout output from the next-stage amplification circuit 21D.
The SR latch 22 holds the comparison output signal Cout. As a result, for example, at the same time as the start of reception of the optical signal Pin, High level is output as the optical signal detection signal SD representing the presence/absence of optical signal input. Once High level is detected as the comparison output signal Cout, the SR latch 22 holds and outputs the level as the optical signal detection signal SD, as a characteristic feature. It is therefore possible to implement the high-speed optical signal detection circuit 20 that immediately responds to signal reception.